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  1. ISF NPDW : Ultra Memory developing 3D DRAM chip using Nano Spice from Pro Plus
  2. Epson Improves GPS Watch Battery Life with Cadence Tensilica Xtensa Processor
  3. Mentor Graphics Launches Broadest Embedded Systems Solution for Industrial Automation
  4. Toshiba to Accelerate Development of Nano Imprint Lithography
  5. JDSU Introduces New Laser Technology for Efficient Materials Processing
  6. Cadence announces complete SoC development environment for new ARM mobile IP suite
  7. Synopsys' New 25G/50G Ethernet Verification IP Enables Next-Generation Gigabit Design
  8. Synopsys' New LPDDR4 Verification IP Accelerates Verification Closure for High-Perfor
  9. ISF -EDA Introducing the eSilicon(R) IP MarketPlace(TM) Environment
  10. Cadence Announces Verification IP for MIPI SoundWire™ and C-PHY
  11. Allwinner Technology Licenses Arteris Interconnect Fabric IP for Tablet and Mobile De
  12. Synopsys Introduces Dolby MS11 Decoder for DesignWare ARC Audio Processors
  13. New Cadence Energy-Efficient PCI Express IP Helps Reduce Power Consumption for Datace
  14. Syntricity Announces dataConductor 7.1
  15. Latest Release of Synopsys IC Compiler Introduces New Technologies to Further Speed D
  16. Rudolph Technologies Launches S3000SX Transparent Thin Film Metrology System for 28nm
  17. Quartz Imaging Introduces Automated Measurement for Semiconductor...
  18. Invarian: Revolutionizing Full-chip Sign-off Analysis for Complex ICs
  19. Cadence Announces First Commercially Available Design IP and Verification IP for Mobi
  20. Cadence Announces First Commercially Available Design IP and Verification IP for Mobi
  21. Mentor Graphics Announces Flowmaster Thermal Analysis Tool with New Capabilities for
  22. Synopsys Announces Energy-Efficient 28-nm PCI Express 3.0 PHY with Support for 10GBAS
  23. Synopsys' LightTools 8.0 Increases Designer Productivity with Faster Performance and
  24. Synopsys Accelerates Adoption of FinFET Technology with Delivery of Production-Proven
  25. Mentor Graphics Launches New T3Ster DynTIM Tester to Deliver Unrivaled Thermal Interf
  26. Arasan Chip Systems Announces MIPI® Conformant Camera Serial...
  27. Cortina Delivers Industry's First 28nm EDC PHY Architecture
  28. QuickLogic's ArcticLink III VX5 Solution Bridges DragonBoard's MIPI-DSI Interface to
  29. Atrenta Ships 5.0 Release of SpyGlass® Platform
  30. Advantest Develops Mask Defect Review SEM E5610 For Next-Generation Photomasks
  31. Advantest Develops EB Lithography System for 1Xnm Node
  32. X-FAB Announces First 200V SOI Foundry Technology
  33. ISF- PR -EDA -SMIC Unveils 0.13um-1.2V Low-Power Embedded EEPROM Platform
  34. ISF- PR -EDA - Kalray Announces First Samples of MPPA-256 Processor in 28nm
  35. ISF- PR -EDA - ZMDI, Announces the Release of the ZIOL2211 in a Wafe
  36. ISF-PR- EDAJPSA Introduces New IX-6100-MD (Metal Dicing) System
  37. ISF-EDA- 90 NM : TSMC Unveils Foundry's First 100MHz Access Speed Embedded Flash IP
  38. ISF- PR-EDA Nimbula & MapR Tech Deliver the Industry's First Turnkey Hadoop Solution
  39. ISF -PR -EDA - Averna Announces Proligent Release 6.0
  40. Cadence Adds Powerful New Capabilities to Its PCI Express Verification IP Including P
  41. ISF- PR-EDA Altera Reduces Design Complexity in High-Performance 40GbE/100GbE Designs
  42. Advantest Introduces Industry's Highest Capability 3-in-1 Semiconductor Test Clock Mo
  43. Cadence Announces Updated Design and Verification IP for DDR PHY Interface
  44. TI introduces industry's first SAR ADC with SPICE model
  45. Cadence Introduces New NVM Express IP Solutions for Solid State Storage Applications
  46. Cadence Expands System and SoC Verification Offerings to Accelerate System Integratio
  47. ISF- PR-EDA - -ALTIS SEMI Releases Process Design Kits for 130Nm Speci
  48. Anritsu Introduces Tracking Generator with CW Generator for Spectrum Master(TM) MS271
  49. Arasan Chip Systems Announces MIPI® compliant Low Latency...
  50. Cadence OrCAD Capture Marketplace Now Available on Desktop Browsers
  51. Apache Design Releases Fourth-Generation RedHawk for Sub-20 Nanometer Power Sign-off
  52. Cadence Announces TripleCheck IP Validator for Faster IP Compliance Testing
  53. Synopsys Unveils 3D-IC Initiative
  54. ISF -PR -EDA - Altera's Stratix V FPGAs Break Through Performance Barriers
  55. Synopsys Introduces Industry's First 28-nm Multi-Gear MIPI Alliance M-PHY IP Supporti
  56. Synopsys Unveils Next-Generation Verification IP for Faster SoC Verification
  57. Synopsys Announces Design Ware Embedded Memories,logic lib for TSMC 28 -Nano process
  58. Synopsys Announces Industry's First HDMI 1.4 PHY IP in 28-nanometer Processes